Joining a global leader in optical solutions, you’ll be working on adding intelligence to light and passion to innovation, working to enrich people’s lives. Their DNA is defined by imagination, engineering know-how and the ability to provide global industrial capacity in sensor and light technologies.
An experienced verification engineer, you will be responsible for design verification and validation of integrated circuits, using both directed tests and constrained random regressions with a primary focus on mixed signal design verification, but with some proficiency with digital design verification (including UVM)
Technical and team leadership – both within the internal project DV team, but also directly supporting demanding customers – with go hand-in-hand with creation of test benches and automated verification simulations
REQUIREMENTS for THE ROLE
- Master’s degree in Electrical Engineering with 15 years of experience – including at least 5 years in team or technology leadership role with an emphasis in analog/mixed-signal verification
- Experience with technical leadership in mixed signal design verification, block level model specifications, simulation, system verilog real number modeling, etc.
- System Verilog / UVM based DV experience
- Collaborative and respectful team player with mentoring skills, and passionate about the team’s success
- Excellent communication skills (both oral and written) are required, as customer level technical interface and design / team leadership is necessary sometimes under high pressure situations.
- Experience with relevant CAD tools (including Cadence Virtuoso, SPICE, etc.)
- Ability to read analog schematics and extract related main functionality.
- Experience modeling mixed signal/RF blocks including biasing networks, power regulators, bandgaps, Opamp’s, OTA’s, data converters, LNA, PA, mixers, couplers, splitters, combiners, etc…
- Excellent team player – as the role requires internal team leadership.
If you’d like to learn more, get in touch with us here.